Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 227
PCI Express Non-Transparent Bridge
3.19.4.27 SLTCON: PCI Express Slot Control Register
The Slot Control register identifies the PCI Express specific slot control parameters for
operations such as Hot-plug and Power Management.
Register:SLTCON
Bus:0
Device:3
Function:0
Offset:1A8h
Bit Attr Default Description
15:13 RsvdP 0h
Reserved.
12 RWS 0
Data Link Layer State Changed Enable: When set to 1, this field enables
software notification when Data Link Layer Link Active field is changed
11 WO 0
Electromechanical Interlock Control
When software writes either a 1 to this bit, IIO pulses the EMIL pin per PCI
Express Server/Workstation Module Electromechanical Spec, Revision 1.0.
Write of 0 has no effect. This bit always returns a 0 when read. If
electromechanical lock is not implemented, then either a write of 1 or 0 to
this register has no effect.
10 RWS 1
Power Controller Control
if a power controller is implemented, when written sets the power state of
the slot per the defined encodings. Reads of this field must reflect the value
from the latest write, even if the corresponding hot-plug command is not
executed yet at the VPP, unless software issues a write without waiting for
the previous command to complete in which case the read value is
undefined.
0: Power On
1: Power Off
9:8 RW 3h
Power Indicator Control
If a Power Indicator is implemented, writes to this register set the Power
Indicator to the written state. Reads of this field must reflect the value from
the latest write, even if the corresponding hot-plug command is not executed
yet at the VPP, unless software issues a write without waiting for the
previous command to complete in which case the read value is undefined.
00: Reserved.
01: On
10: Blink (IIO drives 1.5 Hz square wave for Chassis mounted LEDs)
11: Off
When this register is written, the event is signaled via the virtual pins
1
of the
IIO over a dedicated SMBus port.
IIO does not generated the Power_Indicator_On/Off/Blink messages on PCI
Express when this field is written to by software.
7:6 RW 3h
Attention Indicator Control
If an Attention Indicator is implemented, writes to this register set the
Attention Indicator to the written state.
Reads of this field reflect the value from the latest write, even if the
corresponding hot-plug command is not executed yet at the VPP, unless
software issues a write without waiting for the previous command to
complete in which case the read value is undefined.
00: Reserved.
01: On
10: Blink (The IIO drives 1.5 Hz square wave)
11: Off
When this register is written, the event is signaled via the virtual pins
2
of the
IIO over a dedicated SMBus port.
IIO does not generated the Attention_Indicator_On/Off/Blink messages on
PCI Express when this field is written to by software.