Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 225
PCI Express Non-Transparent Bridge
3.19.4.26 SLTCAP: PCI Express Slot Capabilities Register
The Slot Capabilities register identifies the PCI Express specific slot capabilities.
Register:SLTCAP
Bus:0
Device:3
Function:0
Offset:1A4h
Bit Attr Default Description
31:19 RWO 0h
Physical Slot Number
This field indicates the physical slot number of the slot connected to the PCI
Express port and is initialized by BIOS.
18 RO 0h
Command Complete Not Capable: IIO is capable of command complete
interrupt.
17 RWO 0h
Electromechanical Interlock Present
This bit when set indicates that an Electromechanical Interlock is implemented
on the chassis for this slot and that lock is controlled by bit 11 in Slot Control
register.
BIOS note: EMIL has been defeatured per DCN 430354. BIOS must write a 0
to this bit to lockout EMIL.
16:15 RWO 0h
Slot Power Limit Scale
This field specifies the scale used for the Slot Power Limit Value and is
initialized by BIOS. IIO uses this field when it sends a Set_Slot_Power_Limit
message on PCI Express.
Range of Values:
00: 1.0x
01: 0.1x
10: 0.01x
11: 0.001x
14:7 RWO 00h
Slot Power Limit Value
This field specifies the upper limit on power supplied by slot in conjunction
with the Slot Power Limit Scale value defined previously
Power limit (in Watts) = SPLS x SPLV.
This field is initialized by BIOS. IIO uses this field when it sends a
Set_Slot_Power_Limit message on PCI Express.
6RWO 0h
Hot-plug Capable
This field defines hot-plug support capabilities for the PCI Express port.
0: indicates that this slot is not capable of supporting Hot-plug operations.
1: indicates that this slot is capable of supporting Hot-plug operations
This bit is programed by BIOS based on the system design. This bit must be
programmed by BIOS to be consistent with the VPP enable bit for the port.
5RWO 0h
Hot-plug Surprise
This field indicates that a device in this slot may be removed from the system
without prior notification (like for instance a PCI Express cable).
0: indicates that hot-plug surprise is not supported
1: indicates that hot-plug surprise is supported
If platform implemented cable solution (either direct or via a SIOM with
repeater), on a port, then this could be set. BIOS programs this field with a 0
for CEM/SIOM FFs.
This bit is used by IIO hardware to determine if a transition from DL_active to
DL_Inactive is to be treated as a surprise down error or not. If a port is
associated with a hot pluggable slot and the hotplug surprise bit is set, then
any transition to DL_Inactive is not considered an error. See the PCI Express
Base Specification, Revision 2.0 for further details.