Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
224 Order Number: 323103-001
11 RO 0
Link Training
This field indicates the status of an ongoing link training session in the PCI
Express port
0: LTSSM has exited the recovery/configuration state
1: LTSSM is in recovery/configuration state or the Retrain Link was set but
training has not yet begun.
The IIO hardware clears this bit once LTSSM has exited the recovery/
configuration state. See the PCI Express Base Specification, Revision 2.0 for
details of which states within the LTSSM would set this bit and which states
would clear this bit.
10 RO 0 Reserved
9:4 RO 0h
Negotiated Link Width
This field indicates the negotiated width of the given PCI Express link after
training is completed.
Defined encodings are:
00 0001b: x1
00 0010b: x2
00 0100b: x4
00 1000b: x8
01 0000b: x16
All other encodings are reserved
The value in this field is reserved and could show any value when the link is
not up. Software determines if the link is up or not by reading bit 13 of this
register.
3:0 RO 1h
Current Link Speed
This field indicates the negotiated Link speed of the given PCI Express Link.
0001- 2.5 Gbps
0010 - 5Gbps (IIO will never set this value when Gen2_OFF fuse is blown)
Others - Reserved
The value in this field is not defined and could show any value, when the link is
not up. Software determines if the link is up or not by reading bit 13 of this
register.
Register:LNKSTS
Bus:0
Device:3
Function:0
Offset:1A2h
Bit Attr Default Description