Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 223
PCI Express Non-Transparent Bridge
3.19.4.25 LNKSTS: PCI Express Link Status Register
The PCI Express Link Status register provides information on the status of the PCI
Express Link such as negotiated width, training etc. The link status register needs some
default values setup by the local host. This register has been created to provide a back
door path to program the link status from the primary side. The link status register on
the secondary side of the NTB is located at Section 3.20.3.22, “LNKSTS: PCI Express
Link Status Register” .
Register:LNKSTS
Bus:0
Device:3
Function:0
Offset:1A2h
Bit Attr Default Description
15
RW1
C
0
Link Autonomous Bandwidth Status: This bit is not applicable and is
reserved for Endpoints
14
RW1
C
0
Link Bandwidth Management Status: This bit is not applicable and is
reserved for Endpoints
13 RO 0
Data Link Layer Link Active
Set to 1b when the Data Link Control and Management State Machine is in the
DL_Active state, 0b otherwise.
On a downstream port or upstream port, when this bit is 0b, the transaction
layer associated with the link will abort all transactions that would otherwise
be routed to that link.
12 RWO 1
Slot Clock Configuration
This bit indicates whether IIO receives clock from the same xtal that also
provides clock to the device on the other end of the link.
1: indicates that same xtal provides clocks to devices on both ends of the link
0: indicates that different xtals provide clocks to devices on both ends of the
link
Note: