Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
222 Order Number: 323103-001
04 RWL 0b
Link Disable
This bit is not applicable and is reserved for Endpoints
Note: Appears to SW as RO
03 RO 0b
Read Completion Boundary
Set to zero to indicate IIO could return read completions at 64B boundaries
Note: NTB is not PCIE compliant in this respect. NTB is only capable of 64B
RCB. If connecting to non IA IP and the IP does the optional 128B
RCB check on received packets, packets will be seen as malformed.
This is not an issue with any Intel IP.
02 RsvdP 0b Reserved.
01:00 RW 00b
Active State Link PM Control: When 01b or 11b, L0s on transmitter is
enabled, otherwise it is disabled.
Defined encodings are:
00b Disabled
01b L0s Entry Enabled
10b L1 Entry Enabled
11b L0s and L1 Entry Enabled
Note: “L0s Entry Enabled” indicates the Transmitter entering L0s is
supported. The Receiver must be capable of entering L0s even when
the field is disabled (00b).
ASPM L1 must be enabled by software in the Upstream component on a Link
prior to enabling ASPM L1 in the Downstream component on that Link. When
disabling ASPM L1, software must disable ASPM L1 in the Downstream
component on a Link prior to disabling ASPM L1 in the Upstream component
on that Link. ASPM L1 must only be enabled on the Downstream component
if both components on a Link support ASPM L1.
Register:LNKCON
Bus:0
Device:3
Function:0
Offset:1A0h
Bit Attr Default Description