Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 221
PCI Express Non-Transparent Bridge
3.19.4.24 LNKCON: PCI Express Link Control Register
The PCI Express Link Control register controls the PCI Express Link specific parameters.
The link control register needs some default values setup by the local host. This
register has been created to provide a back door path to program the link control
register from the primary side. The link control register on the secondary side of the
NTB is located at Section 3.20.3.21, “LNKCON: PCI Express Link Control Register”
In NTB/RP mode RP will program this register. In NTB/NTB mode local host BIOS will
program this register.
Register:LNKCON
Bus:0
Device:3
Function:0
Offset:1A0h
Bit Attr Default Description
15:12 RsvdP 0h Reserved
11 RW 0b
Link Autonomous Bandwidth Interrupt Enable - This bit is not
applicable and is reserved for Endpoints
10 RW 0b
Link Bandwidth Management Interrupt Enable - This bit is not
applicable and is reserved for Endpoints
09 RW 0b
Hardware Autonomous Width Disable - IIO never changes a configured
link width for reasons other than reliability.
08 RO 0b Enable Clock Power Management N/A to IIO
07 RW 0b
Extended Synch
This bit when set forces the transmission of additional ordered sets when
exiting L0s and when in recovery. See PCI Express Base Specification,
Revision 2.0 for details.
06 RW 0b
Common Clock Configuration
IIO does nothing with this bit
05 WO 0b
Retrain Link
A write of 1 to this bit initiates link retraining in the given PCI Express port
by directing the LTSSM to the recovery state if the current state is [L0, L0s or
L1]. If the current state is anything other than L0, L0s, L1 then a write to
this bit does nothing. This bit always returns 0 when read.
If the Target Link Speed field has been set to a non-zero value different than
the current operating speed, then the LTSSM will attempt to negotiate to the
target link speed.
It is permitted to write 1b to this bit while simultaneously writing modified
values to other fields in this register. When this is done, all modified values
that affect link retraining must be applied in the subsequent retraining.
Note: Hardware clears this bit on next clock after it is written.