Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 219
PCI Express Non-Transparent Bridge
3.19.4.23 LNKCAP: PCI Express Link Capabilities Register
The Link Capabilities register identifies the PCI Express specific link capabilities
The link capabilities register needs some default values setup by the local host. This
register has been created to provide a back door path to program the link capabilities
from the primary side. The link capabilities register on the secondary side of the NTB is
located at Section 3.20.3.20, “LNKCAP: PCI Express Link Capabilities Register” .
Register:LNKCAP
Bus:0
Device:3
Function:0
Offset:19Ch
Bit Attr Default Description
31:24 RWO 0
Port Number
This field indicates the PCI Express port number for the link and is
initialized by software/BIOS.
23:22 RsvdP 0h
Reserved.
21 RO 1
Link Bandwidth Notification Capability - A value of 1b indicates
support for the Link Bandwidth Notification status and interrupt
mechanisms.
20 RO 1
Data Link Layer Link Active Reporting Capable: IIO supports
reporting status of the data link layer so software knows when it can
enumerate a device on the link or otherwise know the status of the link.
19 RO 1
Surprise Down Error Reporting Capable: IIO supports reporting a
surprise down error condition
18 RO 0 Clock Power Management: Does not apply to IIO.
17:15 RWO 010
L1 Exit Latency
This field indicates the L1 exit latency for the given PCI-Express port. It
indicates the length of time this port requires to complete transition from
L1 to L0.
000: Less than 1 us
001: 1 us to less than 2 us
010: 2 us to less than 4 us
011: 4 us to less than 8 us
100: 8 us to less than 16 us
101: 16 us to less than 32 us
110: 32 us to 64 us
111: More than 64us