Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
216 Order Number: 323103-001
3.19.4.18 ACSCTRL: Access Control Services Control Register
This register identifies the Access Control Services (ACS) control bits.
3.19.4.19 PERFCTRLSTS: Performance Control and Status Register
BDF 030 Offset 180H. This register exist in both RP and NTB modes. It is documented
in RP Section 3.4.5.18, “PERFCTRLSTS: Performance Control and Status Register”. See
Volume 2 of the Datasheet.
3.19.4.20 MISCCTRLSTS: Misc. Control and Status Register
BDF 030 Offset 188H. This register exist in both RP and NTB modes. It is documented
in RP Section 22.5.6.24, “MISCCTRLSTS: Misc. Control and Status Register (Dev#0,
PCIe Mode and Dev#3-6)” in Volume 2 of the Datasheet.
Register:ACSCTRL
Bus:0
Device:3
Function:0
Offset:156h
Bit Attr Default Description
15:7 RO 0 Reserved.
6RO 0
ACS Direct Translated P2P Enable (T)
This is hardwired to 0b as the component does not implement ACS Direct
Translated P2P.
5RO 0
ACS P2P Egress Control Enable (E)
This is hardwired to 0b as the component does not implement ACS P2P Egress
Control.
4RWL 0
ACS Upstream Forwarding Enable (U)
When set, the component forwards upstream any Request or Completion TLPs
it receives that were redirected upstream by a component lower in the
hierarchy.
The U bit only applies to upstream TLPs arriving at a Downstream Port, and
whose normal routing targets the same Downstream Port.
Note: When in NTB mode, this register bit is locked RO =0. See bits 1:0 of
“PPD: PCIE Port Definition” on page 203
3RWL 0
ACS P2P Completion Redirect Enable (C)
Determines when the component redirects peer-to-peer Completions
upstream; applicable only to Read Completions whose Relaxed Ordering
Attribute is clear.
Note: When in NTB mode, this register bit is locked RO =0. See bits 1:0 of
“PPD: PCIE Port Definition” on page 203
2RWL 0
ACS P2P Request Redirect Enable (R)
This bit determines when the component redirects peer-to-peer Requests
upstream.
Note: When in NTB mode, this register bit is locked RO =0. See bits 1:0 of
“PPD: PCIE Port Definition” on page 203
1RWL 0
ACS Translation Blocking Enable (B)
When set, the component blocks all upstream Memory Requests whose
Address Translation (AT) field is not set to the default value.
Note: When in NTB mode, this register bit is locked RO =0. See bits 1:0 of
“PPD: PCIE Port Definition” on page 203
0RWL 0
ACS Source Validation Enable (V)
When set, the component validates the Bus Number from the Requester ID of
upstream Requests against the secondary / subordinate Bus Numbers.
Note: When in NTB mode, this register bit is locked RO =0. See bits 1:0 of
“PPD: PCIE Port Definition” on page 203