Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 215
PCI Express Non-Transparent Bridge
3.19.4.14 APICBASE: APIC Base Register
BDF 030 Offset 140H. This register exist in both RP and NTB modes. It is documented
in RP Section 3.4.5.13, “APICBASE: APIC Base Register”. See Volume 2 of the
Datasheet.
3.19.4.15 APICLIMIT: APIC Limit Register
BDF 030 Offset 142H. This register exist in both RP and NTB modes. It is documented
in RP Section 3.4.5.14, “APICLIMIT: APIC Limit Register”. See Volume 2 of the
Datasheet.
3.19.4.16 ACSCAPHDR: Access Control Services Extended Capability Header
BDF 030 Offset 150H. This register exist in both RP and NTB modes. It is documented
in RP Section 3.4.5.15, “ACSCAPHDR: Access Control Services Extended Capability
Header”. See Volume 2 of the Datasheet.
3.19.4.17 ACSCAP: Access Control Services Capability Register
This register identifies the Access Control Services (ACS) capabilities.
Register:ACSCAP
Bus:0
Device:3
Function:0
Offset:154h
Bit Attr Default Description
15:8 RO 00h
Egress Control Vector Size
Indicates the number of bits in the Egress Control Vector. This is set to 00h as
ACS P2P Egress Control (E) bit in this register is 0b.
7RO 0 Reserved.
6RO 0
ACS Direct Translated P2P (T)
Indicates that the component does not implement ACS Direct Translated P2P.
5RO 0
ACS P2P Egress Control (E)
Indicates that the component does not implement ACS P2P Egress Control.
4RO 0
ACS Upstream Forwarding (U)
Indicates that the component implements ACS Upstream Forwarding.
3RO 0
ACS P2P Completion Redirect (C)
Indicates that the component implements ACS P2P Completion Redirect.
2RO 0
ACS P2P Request Redirect (R)
Indicates that the component implements ACS P2P Request Redirect.
1RO 0
ACS Translation Blocking (B)
Indicates that the component implements ACS Translation Blocking.
0RO 0
ACS Source Validation (V)
Indicates that the component implements ACS Source Validation.