Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
214 Order Number: 323103-001
3.19.4.12 ERRSID: Error Source Identification Register
3.19.4.13 SSMSK: Stop and Scream Mask Register
This register masks uncorrectable errors from being signaled as Stop and Scream
events. Whenever the uncorrectable status bit is set and stop and scream mask is not
set for that bit, it will trigger a Stop and Scream event.
.
Register:ERRSID
Bus:0
Device:3
Function:0
Offset:138h
Bit Attr Default Description
31:16 ROS 0h
Fatal Non Fatal Error Source ID
Requestor ID of the source when an Fatal or Non Fatal error message is
received and the Error Fatal/Nonfatal Received bit is not already set. i.e log
ID of the first Fatal or Non Fatal error message. When the RP itself is the
cause of the received message (virtual message), then a Source ID of
IIOBUSNO:DevNo:0 is logged into this register.
15:0 ROS 0h
Correctable Error Source ID
Requestor ID of the source when a correctable error message is received and
the Correctable Error Received bit is not already set. i.e log ID of the first
correctable error message. When the RP itself is the cause of the received
message (virtual message), then a Source ID of IIOBUSNO:DevNo:0 is
logged into this register.
Register:SSMSK
Bus:0
Device:3
Function:0
Offset:13Ch
Bit Attr Default Description
31:22 RV 0h Reserved
21 RWS 0 ACS Violation Mask
20 RWS 0 Unsupported Request Error Mask
19 RV 0 Reserved
18 RWS 0 Malformed TLP Status
17 RWS 0 Receiver Buffer Overflow Mask
16 RWS 0 Unexpected Completion Mask
15 RWS 0 Completer Abort Status
14 RWS 0 Completion Time-out Mask
13 RWS 0 Flow Control Protocol Error Mask
12 RWS 0 Poisoned TLP Mask
11:6 RV 0h Reserved
5RWS 0Surprise Down Error Mask
4RWS 0Data Link Layer Protocol Error Mask
3:1 RV 000 Reserved
0RO 0Reserved