Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 213
PCI Express Non-Transparent Bridge
Register:RPERRSTS
Bus:0
Device:3
Function:0
Offset:134h
Bit Attr Default Description
31:27 RO 0h
Advanced Error Interrupt Message Number
Advanced Error Interrupt Message Number offset between base message
data an the MSI/MSI-X message if assigned more than one message
number. IIO hardware automatically updates this register to 0x1h if the
number of messages allocated to the RP is 2. See bit 6:4 in Section
3.19.3.3, “MSICTRL: MSI Control Register” on page 187 for details of the
number of messages allocated to a RP.
26:7 RO 0 Reserved
6 RW1CS 0
Fatal Error Messages Received
Set when one or more Fatal Uncorrectable error Messages have been
received.
5 RW1CS 0
Non-Fatal Error Messages Received
Set when one or more Non-Fatal Uncorrectable error Messages have been
received.
4 RW1CS 0
First Uncorrectable Fatal
Set when bit 2 is set (from being clear) and the message causing bit 2 to
be set is an ERR_FATAL message.
3 RW1CS 0
Multiple Error Fatal/Nonfatal Received
Set when either a fatal or a non-fatal error message is received and Error
Fatal/Nonfatal Received is already set, i.e log from the 2nd Fatal or No
fatal error message onwards
2 RW1CS 0
Error Fatal/Nonfatal Received
Set when either a fatal or a non-fatal error message is received and this
bit is already not set. i.e. log the first error message. When this bit is set,
bit 3 could be either set or clear.
1 RW1CS 0
Multiple Correctable Error Received
Set when either a correctable error message is received and Correctable
Error Received bit is already set, i.e log from the 2nd Correctable error
message onwards
0 RW1CS 0
Correctable Error Received
Set when a correctable error message is received and this bit is already
not set. i.e. log the first error message