Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
212 Order Number: 323103-001
3.19.4.10 RPERRCMD: Root Port Error Command Register
This register controls behavior upon detection of errors.
3.19.4.11 RPERRSTS: Root Port Error Status Register
The Root Error Status register reports status of error Messages (ERR_COR,
ERR_NONFATAL, and ERR_FATAL) received by the Root Complex in IIO, and errors
detected by the RP itself (which are treated conceptually as if the RP had sent an error
Message to itself). The ERR_NONFATAL and ERR_FATAL Messages are grouped together
as uncorrectable. Each correctable and uncorrectable (Non-fatal and Fatal) error source
has a first error bit and a next error bit associated with it respectively. When an error is
received by a Root Complex, the respective first error bit is set and the Requestor ID is
logged in the Error Source Identification register. A set individual error status bit
indicates that a particular error category occurred; software may clear an error status
by writing a 1 to the respective bit. If software does not clear the first reported error
before another error Message is received of the same category (correctable or
uncorrectable), the corresponding next error status bit will be set but the Requestor ID
of the subsequent error Message is discarded. The next error status bits may be
cleared by software by writing a 1 to the respective bit as well.
Register:ERRCMD
Bus:0
Device:3
Function:0
Offset:130h
Bit Attr Default Description
31:3 RV 0h Reserved
2RW 0
FATAL Error Reporting Enable
Enable MSI/MSI-X interrupt on fatal errors when set. See Section 11.6,
“IIO Errors Handling Summary” (IOH Platform Architecture Specification)
for details of MSI/MSI-X generation for PCI Express error events.
1RW 0
Non-FATAL Error Reporting Enable
Enable interrupt on a non-fatal error when set. See Section 11.6, “IIO
Errors Handling Summary” (IOH Platform Architecture Specification) for
details of MSI/MSI-X generation for PCI Express error events.
0RW 0
Correctable Error Reporting Enable
Enable interrupt on correctable errors when set. See Section 11.6, “IIO
Errors Handling Summary” (IOH Platform Architecture Specification) for
details of MSI/MSI-X generation for PCI Express error events.