Datasheet

Intel

Xeon

Processor C5500/C3500 Series

February 2010 Datasheet, Volume 1

Order Number: 323103-001 211

PCI Express Non-Transparent Bridge

3.19.4.8 ERRCAP: Advanced Error Capabilities and Control Register

3.19.4.9 HDRLOG: Header Log

This register contains the header log when the first error occurs. Headers of the

subsequent errors are not logged.

Bus:0

Device:3

Function:0

Offset:11Ch

Bit Attr Default Description

31:9 RV 0h Reserved

8RO 0ECRC Check Enable: N/A to IIO

7RO 0ECRC Check Capable: N/A to IIO

6RO 0ECRC Generation Enable: N/A to IIO

5RO 0ECRC Generation Capable: N/A to IIO

4:0 ROS 0h

First error pointer

The First Error Pointer is a read-only register that identifies the bit position of

the first unmasked error reported in the Uncorrectable Error register. In case

of two errors happening at the same time, fatal error gets precedence over

non-fatal, in terms of being reported as first error. This field is rearmed to

capture new errors when the status bit indicated by this field is cleared by

software.

Bus:0

Device:3

Function:0

Offset:120h

Bit Attr Default Description

127:0 ROS 0h Header of TLP associated with error