Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
210 Order Number: 323103-001
3.19.4.6 CORERRSTS: Correctable Error Status
This register identifies the status of the correctable errors that have been detected by
the PCI Express port.
3.19.4.7 CORERRMSK: Correctable Error Mask
This register masks correctable errors from being signaled.
Register:CORERRSTS
Bus:0
Device:3
Function:0
Offset:114h
Bit Attr Default Description
31:14 RV 0h Reserved
13 RW1CS 0 Advisory Non-fatal Error Status
12 RW1CS 0 Replay Timer Time-out Status
11:9 RV 0h Reserved
8 RW1CS 0 Replay_Num Rollover Status
7 RW1CS 0 Bad DLLP Status
6 RW1CS 0 Bad TLP Status
5:1 RV 0h Reserved
0 RW1CS 0 Receiver Error Status
Register:CORERRMSK
Bus:0
Device:3
Function:0
Offset:118h
Bit Attr Default Description
31:14 RV 0h Reserved
13 RWS 1 Advisory Non-fatal Error Mask
12 RWS 0 Replay Timer Time-out Mask
11:9 RV 0h Reserved
8RWS 0Replay_Num Rollover Mask
7RWS 0Bad DLLP Mask
6RWS 0Bad TLP Mask
5:1 RV 0h Reserved
0RWS 0Receiver Error Mask