Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 207
PCI Express Non-Transparent Bridge
3.19.4.2 VSHDR: Vender Specific Header
This register identifies the capability structure and points to the next structure.
3.19.4.3 UNCERRSTS: Uncorrectable Error Status
This register identifies uncorrectable errors detected for PCI Express/DMI port.
Register:VSHDR
Bus:0
Device:3
Function:0
Offset:104h
Bit Attr Default Description
31:20 RO 03Ch
VSEC Length
This field indicates the number of bytes in the entire VSEC structure, including
the PCI Express Enhanced Capability header, the Vendor-Specific header, and
the Vendor-Specific Registers.
19:16 RO 1h
VSEC Version
Set to 1h for this version of the PCI Express logic
15:0 RO 0004h
VSEC ID
Identifies Intel Vendor Specific Capability for AER on NTB
Register:UNCERRSTS
Bus:0
Device:3
Function:0
Offset:108h
Bit Attr Default Description
31:22 RsvdZ 0h Reserved
21 RW1CS 0 ACS Violation Status
20 RW1CS 0 Received an Unsupported Request
19 RsvdZ 0 Reserved
18 RW1CS 0 Malformed TLP Status
17 RW1CS 0 Receiver Buffer Overflow Status
16 RW1CS 0 Unexpected Completion Status
15 RW1CS 0 Completer Abort Status
14 RW1CS 0 Completion Time-out Status
13 RW1CS 0 Flow Control Protocol Error Status
12 RW1CS 0 Poisoned TLP Status
11:6 RsvdZ 0h Reserved
5 RW1CS 0 Surprise Down Error Status
4 RW1CS 0 Data Link Protocol Error Status
3:1 RsvdZ 0h Reserved
0RO 0Reserved