Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 205
PCI Express Non-Transparent Bridge
3.19.3.25 PMCSR: Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express
port of the IIO.
Register:PMCSR
Bus:0
Device:3
Function:0
Offset:E4h
Bit Attr Default Description
31:24 RO 00h
Data
Not relevant for IIO
23 RO 0h
Bus Power/Clock Control Enable
This field is hardwired to 0h as it does not apply to PCI Express.
22 RO 0h
B2/B3 Support
This field is hardwired to 0h as it does not apply to PCI Express.
21:16 RsvdP 0h Reserved.
15 RW1CS 0h
PME Status
Applies only to RPs
This bit has no meaning for NTB
14:13 RO 0h
Data Scale
Not relevant for IIO
12:9 RO 0h
Data Select
Not relevant for IIO
8 RWS 0h
PME Enable
Applies only to RPs.
0: Disable ability to send PME messages when an event occurs
1: Enables ability to send PME messages when an event occurs
This bit has no meaning for NTB
7:4 RsvdP 0h Reserved.
3RWO 1
No Soft Reset
Indicates IIO does not reset its registers when transitioning from D3hot
to D0.
Note: This bit must be written by BIOS to a ‘1’ so that this register bit
cannot be cleared.
2RsvdP 0hReserved.
1:0 RW 0h
Power State
This 2-bit field is used to determine the current power state of the
function and to set a new power state as well.
00: D0
01: D1 (not supported by IIO)
10: D2 (not supported by IIO)
11: D3_hot
If software tries to write 01 or 10 to this field, the power state does not
change from the existing power state (which is either D0 or D3hot) and
nor do these bits1:0 change value.
All devices will respond to only Type 0 configuration transactions when in
D3hot state (RP will not forward Type 1 accesses to the downstream link)
and will not respond to memory/IO transactions (i.e. D3hot state is
equivalent to MSE/IOSE bits being clear) as target and will not generate
any memory/IO/configuration transactions as initiator on the primary bus
(messages are still allowed to pass through).