Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
204 Order Number: 323103-001
3.19.3.24 PMCAP: Power Management Capabilities Register
The PM Capabilities Register defines the capability ID, next pointer and other power
management related support. The following PM registers /capabilities are added for
software compliance.
Register:PMCAP
Bus:0
Device:3
Function:0
Offset:E0h
Bit Attr Default Description
31:27 RO 00000b
PME Support
Indicates the PM states within which the function is capable of sending a PME
message.
NTB primary side does not forward PME messages.
Bit 31 = D3cold
Bit 30 = D3hot
Bit 29 = D2
Bit 28 = D1
Bit 27 = D0
26 RO 0b
D2 Support
IIO does not support power management state D2.
25 RO 0b
D1 Support
IIO does not support power management state D1.
24:22 RO 000b
AUX Current
Device does not support auxiliary current
21 RO 0b
Device Specific Initialization
Device initialization is not required
20 RV 0b Reserved.
19 RO 0b
PME Clock
This field is hardwired to 0h as it does not apply to PCI Express.
18:16 RO 011b
Version
This field is set to 3h (PM 1.2 compliant) as version number for all PCI Express
ports.
15:8 RO 00h
Next Capability Pointer
This is the last capability in the chain and hence set to 0.
7:0 RO 01h
Capability ID
Provides the PM capability ID assigned by PCI-SIG.