Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 203
PCI Express Non-Transparent Bridge
3.19.3.23 PPD: PCIE Port Definition
This register defines the behavior of the PCIE port which can be either a RP, NTB
connected to another NTB or an NTB connected to a Root Complex.
This register is used to set the value in the DID register on the Primary side of the NTB
(located at offset 02h). This value is loaded by BIOS prior to running PCI enumeration.
Register:PPD
Bus:0
Device:3
Function:0
Offset:0D4h
Bit Attr Default Description
07:06 RO 0h Reserved
05 RW 0b
NTB Primary side - MSI-X Single Message Vector: This bit when set, causes
only a single MSI-X vector to be generated if MSI-X is enabled. This bit affects the
default value of the MSI-X Table Size field in the Section 3.19.3.10,
“MSIXMSGCTRL: MSI-X Message Control Register”
04 RO 0h
Crosslink Configuration Status: This bit is written by hardware and shows the
result of the PE_NTBXL strap combined with the crosslink control override settings.
0 = NTB port is configured as DSD/USP
1 = NTB port is configured as USD/DSP
03:02 RW 00b
Crosslink Control Override: When bit 3 of this register is set, the NTB logic
ignores the setting of the external pin strap (PE_NTBXL) and directly forces the
polarity of the NTB port to be either an Upstream Device (USD) or Downstream
Device (DSD) based on the setting of bit 2.
11 - Force NTB port to USD/DSP; NTB ignores input from PE_NTBXL
10 - Force NTB port to DSD/USP; NTB ignores input from PE_NTBXL
01 - Reserved
00 - Use external pin (PE_NTBXL) only to determine USD or DSD (default)
Note: Bits 03:02 of this register only have meaning when bits 01:00 of this same
register are programmed as “01”b (NTB/NTB). When configured as NTB/RP
hardware directly sets port to DSD/USP so this field is not required.
Note: When using crosslink control override, the external strap PECFGSEL[2:0]
must be set to “100”b (Wait-on-BIOS). The BIOS can then come and set
this field and then enable the port.
Note: In applications that are DP configuration, and having an external controller
set up the crosslink control override through the SMBus master interface.
PECFGSEL[2:0] must be set to “100”b (Wait-on-BIOS) on both chipsets.
The external controller on the master can then set the crosslink control
override field on both chipsets and then enable the ports on both chipsets.
01:00 RW 00b
Port Definition
Value indicating the value to be loaded into the DID register (offset 02h).
00b - Transparent bridge
01b - 2 NTBs connected back to back
10b - NTB connected to a RP
11b - Reserved
Note: When the DISNTSPB fuse is blown this field becomes RO “00”