Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
202 Order Number: 323103-001
3.19.3.21 SBAR23SZ: Secondary BAR 2/3 Size
This register contains a value used to set the size of the memory window requested by
the 64-bit BAR 2/3 pair for the Secondary side of the NTB.
3.19.3.22 SBAR45SZ: Secondary BAR 4/5 Size
This register contains a value used to set the size of the memory window requested by
the 64-bit BAR 4/5 on the secondary side of the NTB.
Register:SBAR23SZ
Bus:0
Device:3
Function:0
Offset:0D2h
Bit Attr Default Description
7:0 RWO 00h
Secondary BAR 2/3 Size
Value indicating the size of 64-bit BAR 2/3 pair on the Secondary side of the NTB.
This value is loaded by BIOS prior to enumeration. The value indicates the number
of bits that will be Read-Only (returning 0 when read regardless of the value written
to them) during PCI enumeration.
Only legal settings are 12- 39, representing BAR sizes of 2
12
(4 KB) through 2
39
(512 GB) are valid.
Note: Programming a value of ‘0’ or any other value other than (12-39) will result
in the BAR being disabled.
Register:SBAR45SZ
Bus:0
Device:3
Function:0
Offset:0D3h
Bit Attr Default Description
7:0 RWO 00h
Secondary BAR 4/5 Size
Value indicating the size of 64-bit BAR 2/3 pair on the Secondary side of the NTB.
This value is loaded by BIOS prior to enumeration. The value indicates the number
of bits that will be Read-Only (returning 0 when read regardless of the value written
to them) during PCI enumeration.
Only legal settings are 12- 39, representing BAR sizes of 2
12
(4 KB) through 2
39
(512 GB) are valid.
Note: Programming a value of ‘0’ or any other value other than (12-39) will result
in the BAR being disabled.