Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 201
PCI Express Non-Transparent Bridge
3.19.3.19 PBAR23SZ: Primary BAR 2/3 Size
This register contains a value used to set the size of the memory window requested by
the 64-bit BAR 2/3 pair for the Primary side of the NTB.
3.19.3.20 PBAR45SZ: Primary BAR 4/5 Size
This register contains a value used to set the size of the memory window requested by
the 64-bit BAR 4/5 pair for the Primary side of the NTB.
Register:PBAR23SZ
Bus:0
Device:3
Function:0
Offset:0D0h
Bit Attr Default Description
7:0 RWO 00h
Primary BAR 2/3 Size
Value indicating the size of 64-bit BAR 2/3 pair on the Primary side of the NTB. This
value is loaded by BIOS prior to enumeration. The value indicates the number of
bits that will be Read-Only (returning 0 when read regardless of the value written to
them) during PCI enumeration.
Only legal settings are 12- 39, representing BAR sizes of 2
12
(4KB) through 2
39
(512GB) are valid.
Note: Programming a value of ‘0’ or any other value other than (12-39) will result
in the BAR being disabled.
Register:PBAR45SZ
Bus:0
Device:3
Function:0
Offset:0D1h
Bit Attr Default Description
7:0 RWO 00h
Primary BAR 4/5 Size
Value indicating the size of 64-bit BAR 2/3 pair. This value is loaded by BIOS prior to
enumeration. The value indicates the number of bits that will be Read-Only
(returning 0 when read regardless of the value written to them) during PCI
enumeration.
Only legal settings are 12- 39, representing BAR sizes of 2
12
(4KB) through 2
39
(512GB) are valid.
Note: Programming a value of ‘0’ or any other value other than (12-39) will result
in the BAR being disabled.