Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 199
PCI Express Non-Transparent Bridge
4 RO 0
Enable Relaxed Ordering
Not applicable since the NTB is never the originator of a TLP.
This bit has no impact on forwarding of relaxed ordering attribute on peer
requests.
3RW 0
Unsupported Request Reporting Enable
Applies only to the PCI Express RP/PCI Express NTB secondary interface/DMI
ports. This bit controls the reporting of unsupported requests that IIO itself
detects on requests its receives from a PCI Express/DMI port.
0: Reporting of unsupported requests is disabled
1: Reporting of unsupported requests is enabled.
2RW 0
Fatal Error Reporting Enable
Applies only to the PCI Express RP/PCI Express NTB secondary interface/DMI
ports. Controls the reporting of fatal errors that IIO detects on the PCI
Express/DMI interface.
0: Reporting of Fatal error detected by device is disabled
1: Reporting of Fatal error detected by device is enabled
1RW 0
Non Fatal Error Reporting Enable
Applies only to the PCI Express RP/PCI Express NTB secondary interface/DMI
ports. Controls the reporting of non-fatal errors that IIO detects on the PCI
Express/DMI interface.
0: Reporting of Non Fatal error detected by device is disabled
1: Reporting of Non Fatal error detected by device is enabled
0RW 0
Correctable Error Reporting Enable
Applies only to the PCI Express RP/PCI Express NTB secondary interface/DMI
ports. Controls the reporting of correctable errors that IIO detects on the PCI
Express/DMI interface
0: Reporting of link Correctable error detected by the port is disabled
1: Reporting of link Correctable error detected by port is enabled
Register:DEVCTRL
Bus:0
Device:3
Function:0
Offset:98h
PCIE_ONLY
Bit Attr Default Description