Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
198 Order Number: 323103-001
3.19.3.17 DEVCTRL: PCI Express Device Control Register (Dev#3, PCIE NTB Pri
Mode)
The PCI Express Device Control register controls PCI Express specific capabilities
parameters associated with the device.
Register:DEVCTRL
Bus:0
Device:3
Function:0
Offset:98h
PCIE_ONLY
Bit Attr Default Description
15 RsvdP 0h Reserved.
14:12
RO 000
Max_Read_Request_Size
This field sets maximum Read Request size generated by the Intel
®
Xeon
®
processor C5500/C3500 series as a requestor. The corresponding IOU logic in
the Intel
®
Xeon
®
processor C5500/C3500 series associated with the
PCIExpress port must not generate read requests with size exceeding the set
value.
000: 128B max read request size
001: 256B max read request size
010: 512B max read request size
011: 1024B max read request size
100: 2048B max read request size
101: 4096B max read request size
110: Reserved
111: Reserved
Note: The Intel
®
Xeon
®
processor C5500/C3500 series will not generate
read requests larger than 64B on the outbound side due to the
internal Micro-architecture (CPU initiated, DMA, or Peer to Peer).
Hence the field is set to 000b encoding.
11 RO 0
Enable No Snoop
Not applicable since the NTB is never the originator of a TLP.
This bit has no impact on forwarding of NoSnoop attribute on peer requests.
10 RO 0
Auxiliary Power Management Enable
Not applicable to IIO
9RO 0
Phantom Functions Enable
Not applicable to IIO since it never uses phantom functions as a requester.
8RW 0h
Extended Tag Field Enable
This bit enables the PCI Express/DMI ports to use an 8-bit Tag field as a
requester.
7:5 RW 000
Max Payload Size
This field is set by configuration software for the maximum TLP payload size
for the PCI Express port. As a receiver, the IIO must handle TLPs as large as
the set value. As a requester (i.e. for requests where IIOs own RequesterID
is used), it must not generate TLPs exceeding the set value. Permissible
values that can be programmed are indicated by the
Max_Payload_Size_Supported in the Device Capabilities register:
000: 128B max payload size
001: 256B max payload size (applies only to standard PCI Express ports and
DMI port aliases to 128B)
others: alias to 128B
This field is RW for PCI Express ports.
Note: Bit 7:5 must be programmed to the same value on both primary and
secondary side of the NTB