Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 195
PCI Express Non-Transparent Bridge
3.19.3.15 PXPCAP: PCI Express Capabilities Register
The PCI Express Capabilities register identifies the PCI Express device type and
associated capabilities.
Register:PXPCAP
Bus:0
Device:3
Function:0
Offset:92h
Bit Attr Default Description
15:14
Rsvd
P
00b Reserved
13:9 RO 00000b
Interrupt Message Number
Applies only to the RPs.
This field indicates the interrupt message number that is generated for PM/HP
events. When there are more than one MSI/MSI-X interrupt Number, this
register field is required to contain the offset between the base Message Data
and the MSI/MSI-X Message that is generated when the status bits in the slot
status register or RP status registers are set. IIO assigns the first vector for
PM/HP events and so this field is set to 0.
8RWO 0b
Slot Implemented
Applies only to the RPs for NTB this value is kept at 0b.
1: indicates that the PCI Express link associated with the port is connected to
a slot.
0: indicates no slot is connected to this port.
This register bit is of type “write once” and is controlled by BIOS/special
initialization firmware.
7:4 RO 0000b
Device/Port Type
This field identifies the type of device.
0000b = PCI Express Endpoint.
3:0 RWO 2h
Capability Version
This field identifies the version of the PCI Express capability structure. Set to
2h for PCI Express devices for compliance with the extended base registers.