Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 193
PCI Express Non-Transparent Bridge
3.19.3.11 TABLEOFF_BIR: MSI-X Table Offset and BAR Indicator Register (BIR)
Register default: 00002000h
3.19.3.12 PBAOFF_BIR: MSI-X Pending Array Offset and BAR Indicator
Register default: 00003000h
Register:TABLEOFF_BIR
Bus:0
Device:3
Function:0
Offset:84h
Bit Attr Default Description
31:03 RO 00000400h
Table Offset
MSI-X Table Structure is at offset 8K from the PB01BASE address. See
Section 3.19.3.13, “PXPCAPID: PCI Express Capability Identity Register” for
the start of details relating to MSI-X registers.
02:00 RO 0h
Table BIR
Indicates which one of a function’s Base Address registers, located beginning
at 10h in Configuration Space, is used to map the function’s MSI-X Table into
Memory Space.
BIR Value Base Address register
0 10h
1 14h
2 18h
3 1Ch
4 20h
5 24h
6 Reserved
7 Reserved
For a 64-bit Base Address register, the Table BIR indicates the lower DWORD.
Register:PBAOFF_BIR
Bus:0
Device:3
Function:0
Offset:88h
Bit Attr Default Description
31:03 RO 00000600h
Table Offset
MSI-X PBA Structure is at offset 12K from the PB01BASE BAR address.
Section 3.21.2.4, “PMSIXPBA: Primary MSI-X Pending Bit Array Register” for
details
02:00 RO 0h
PBA BIR
Indicates which one of a function’s Base Address registers, located beginning
at 10h in Configuration Space, is used to map the function’s MSI-X Table into
Memory Space.
BIR Value Base Address register
0 10h
1 14h
2 18h
3 1Ch
4 20h
5 24h
6 Reserved
7 Reserved
For a 64-bit Base Address register, the Table BIR indicates the lower DWORD.