Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
192 Order Number: 323103-001
3.19.3.9 MSIXNXTPTR: MSI-X Next Pointer
3.19.3.10 MSIXMSGCTRL: MSI-X Message Control Register
Register:MSIXNXTPTR
Bus:0
Device:3
Function:0
Offset:81h
Bit Attr Default Description
7:0 RWO 90h
Next Ptr
This field is set to 90h for the next capability list (PCI Express capability
structure) in the chain.
Register:
MSIXMSGCTRL
Bus:0
Device:3
Function:0
Offset:82h
Bit Attr Default Description
15 RW 0b
MSI-X Enable
Software uses this bit to enable MSI-X method for signaling
0: NTB is prohibited from using MSI-X to request service
1: MSI-X method is chosen for NTB interrupts
Note: Software must disable INTx and MSI for this device when using MSI-X
14 RW 0b
Function Mask
If = 1b, all the vectors associated with the NTB are masked, regardless of the
per vector mask bit state.
If = 0b, each vector’s mask bit determines whether the vector is masked or
not. Setting or clearing the MSI-X function mask bit has no effect on the state
of the per-vector Mask bit.
13:11 RO 0h Reserved.
10:00 RO 003h
Table Size
System software reads this field to determine the MSI-X Table Size N, which is
encoded as N-1. For example, a returned value of “00000000011” indicates a
table size of 4.
The value in this field depends on the setting of Section 3.19.3.23, “PPD: PCIE
Port Definition” bit 5.
When PPD, bit 5 = ‘0’ (default) Table size is 4, encoded as a value of 003h
When PPD, bit 5 = ‘1’ Table size is 1, encoded as a value of 000h