Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 191
PCI Express Non-Transparent Bridge
3.19.3.6 MSIMSK: MSI Mask Bit Register
The Mask Bit register enables software to disable message sending on a per-vector
basis.
3.19.3.7 MSIPENDING: MSI Pending Bit Register
The Mask Pending register enables software to defer message sending on a per-vector
basis.
3.19.3.8 MSIXCAPID: MSI-X Capability ID
Register:MSIMSK
Bus:0
Device:3
Function:0
Offset:6Ch
Bit Attr Default Description
31:02 RsvdP 0h Reserved
01:00 RW 00b
Mask Bits
For each Mask bit that is set, the PCI Express port is prohibited from sending
the associated message.
NTB supports up to 2 messages
Corresponding bits are masked if set to ‘1’
Register:MSIPENDING
Bus:0
Device:3
Function:0
Offset:70h
Bit Attr Default Description
31:02 RsvdP 0h Reserved
01:00 RO 0h
Pending Bits
For each Pending bit that is set, the PCI Express port has a pending associated
message.
NTB supports up to 2 messages
Corresponding bits are pending if set to ‘1’
Register:
MSIXCAPID
Bus:0
Device:3
Function:0
Offset:80h
Bit Attr Default Description
7:0 RO 11h
Capability ID
Assigned by PCI-SIG for MSI-X.