Datasheet
PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
190 Order Number: 323103-001
3.19.3.5 MSIDR: MSI Data Register
The MSI Data Register contains all the data (interrupt vector) related to MSI interrupts
from the root ports.
Register:MSIDR
Bus:0
Device:3
Function:0
Offset:68h
Bit Attr Default Description
31:16 RO 0000h Reserved.
15 RW 0h
Trigger Mode
0 - Edge Triggered
1 - Level Triggered
The IIO does nothing with this bit other than passing it along to the Intel
®
QPI
14 RW 0h
Level
0 - Deassert
1 - Assert
The IIO does nothing with this bit other than passing it along to the Intel
®
QPI
13:12 RW 0h
Don’t care for IIO
11:8 RW 0h
Delivery Mode
0000 – Fixed: Trigger Mode can be edge or level.
0001 – Lowest Priority: Trigger Mode can be edge or level.
0010 – SMI/PMI/MCA - Not supported via MSI of root port
0011 – Reserved - Not supported via MSI of root port
0100 – NMI - Not supported via MSI of root port
0101 – INIT - Not supported via MSI of root port
0110 – Reserved
0111 – ExtINT - Not supported via MSI of root port
1000-1111 - Reserved
7:0 RW 0h
Interrupt Vector
The interrupt vector (LSB) will be modified by the IIO to provide context
sensitive interrupt information for different events that require attention from
the processor. e.g Hot plug, Power Management and RAS error events.
Depending on the number of Messages enabled by the processor, Table 91
illustrates how the IIO distributes these vectors.
Table 91. MSI Vector Handling and Processing by IIO on Primary Side
Number of Messages enabled
by Software
Events IV[7:0]
1All
xxxxxxxx
1
1. The term “xxxxxx” in the Interrupt vector denotes that software initializes them and IIO will not modify any
of the “x” bits except the LSB as indicated in the table as a function of MMEN
2
HP, PD[15:00]
xxxxxxx0
AER xxxxxxx1