Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 19
Tables
1 Available SKUs ........................................................................................................27
2 Terminology............................................................................................................32
3 Processor Documents ...............................................................................................33
4 PCH Documents....................................................................................................... 34
5 Public Specifications.................................................................................................34
6 System Memory Feature Summary.............................................................................35
7Intel
®
Xeon
®
Processor C5500/C3500 Series with RDIMM Only Support.......................... 37
8 UDIMM Only Support................................................................................................37
9 DDR3 System Memory Timing Support........................................................................38
10 Mapping from Logical to Physical Channels ..................................................................39
11 RDIMM Population Configurations Within a Channel for Three Slots per Channel ...............46
12 UDIMM Population Configurations Within a Channel for Three Slots per Channel ...............47
13 DIMM Population Configurations Within a Channel for Two Slots per Channel....................47
14 UDIMM Population Configurations Within a Channel for Two Slots per Channel..................48
15 Causes of SMI or NMI...............................................................................................51
16 Read and Write Steering ...........................................................................................53
17 Address Mapping Registers........................................................................................54
18 Critical Word First Sequence of Read Returns...............................................................57
19 Lower System Address Bit Mapping Summary..............................................................57
20 DDR Organizations Supported....................................................................................58
21 DRAM Power Savings Exit Parameters.........................................................................60
22 Dynamic IO Power Savings Features...........................................................................60
23 DDR_THERM# Responses.......................................................................................... 64
24 Refresh for Different DRAM Types ..............................................................................65
25 1 or 2 Single/Dual Rank Throttling..............................................................................67
26 1 or 2 Quad Rank or 3 Single/Dual Rank Throttling.......................................................67
27 Thermal Throttling Control Fields................................................................................68
28 Thermal Throttling Status Fields.................................................................................69
29 Summary of Processor-Specific PECI Commands..........................................................70
30 GetTemp() Response Definition..................................................................................74
31 PCIConfigRd() Response Definition .............................................................................76
32 PCIConfigWr() Device/Function Support ......................................................................76
33 PCIConfigWr() Response Definition.............................................................................77
34 Mailbox Command Summary .....................................................................................78
35 Counter Definition....................................................................................................79
36 Machine Check Bank Definitions................................................................................. 81
37 ACPI T-State Duty Cycle Definition .............................................................................82
38 MbxSend() Response Definition..................................................................................84
39 MbxGet() Response Definition....................................................................................85
40 Domain ID Definition................................................................................................87
41 Multi-Domain Command Code Reference.....................................................................87
42 Completion Code Pass/Fail Mask ................................................................................ 87
43 Device Specific Completion Code (CC) Definition ..........................................................88
44 Originator Response Guidelines.................................................................................. 88
45 Error Codes and Descriptions.....................................................................................90
46 PECI Client Response During Power-Up (During ‘Data Not Ready’) ..................................90
47 Power Impact of PECI Commands vs. C-states.............................................................91
48 PECI Client Response During S1.................................................................................92
49 SMBus Command Encoding .......................................................................................94
50 Internal SMBus Protocol Stack ...................................................................................95
51 SMBus Slave Address Format.....................................................................................95
52 Memory Region Address Field ....................................................................................96
53 Status Field Encoding for SMBus Reads.......................................................................97