Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 189
PCI Express Non-Transparent Bridge
3.19.3.4 MSIAR: MSI Address Register
The MSI Address Register (MSIAR) contains the system specific address information to
route MSI interrupts from the root ports and is broken into its constituent fields.
Register:MSIAR
Bus:0
Device:3
Function:0
Offset:64h
Bit Attr Default Description
31:20 RW 0h
Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address. This
field is R/W.
19:12 RW 00h
Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.
11:4 RW 00h
Address Extended Destination ID
This field is not used by IA32 processor .
3RW 0h
Address Redirection Hint
0: directed
1: redirectable
2RW 0h
Address Destination Mode
0: physical
1: logical
1:0 RO 0h Reserved.