Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
188 Order Number: 323103-001
6:4 RW 000b
Multiple Message Enable
Applicable only to PCI Express ports. Software writes to this field to indicate
the number of allocated messages which is aligned to a power of two. When
MSI is enabled, the software will allocate at least one message to the device. A
value of 000 indicates 1 message. See Table 91 for discussion on how the
interrupts are distributed amongst the various sources of interrupt based on
the number of messages allocated by software for the PCI Express NTB port.
Value
Number of Messages Requested
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = Reserved
111b = Reserved
3:1 RO 001b
Multiple Message Capable
IIO’s PCI Express port supports two messages for all internal events.
Value
Number of Messages Requested
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = Reserved
111b = Reserved
0RW 0b
MSI Enable
The software sets this bit to select platform-specific interrupts or transmit MSI
messages.
0: Disables MSI from being generated.
1: Enables the PCI Express port to use MSI messages for RAS, provided bit 4
in Section 3.19.4.20, “MISCCTRLSTS: Misc. Control and Status Register” on
page 216 is clear and also enables the Express port to use MSI messages for
PM and HP events at the root port provided these individual events are not
enabled for ACPI handling (see Section 3.19.4.20, “MISCCTRLSTS: Misc.
Control and Status Register” on page 216) for details.
Note: Software must disable INTx and MSI-X for this device when using MSI
Register:
MSICTRL
Bus:0
Device:3
Function:0
Offset:62h
Bit Attr Default Description