Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 187
PCI Express Non-Transparent Bridge
3.19.3 Device-Specific PCI Configuration Space - 0x40 to 0xFF
3.19.3.1 MSICAPID: MSI Capability ID
3.19.3.2 MSINXTPTR: MSI Next Pointer
3.19.3.3 MSICTRL: MSI Control Register
Register:MSICAPID
Bus:0
Device:3
Function:0
Offset:60h
Bit Attr Default Description
7:0 RO 05h
Capability ID
Assigned by PCI-SIG for MSI.
Register:
MSINXTPTR
Bus:0
Device:3
Function:0
Offset:61h
Bit Attr Default Description
7:0 RWO 80h
Next Ptr
This field is set to 80h for the next capability list (PCI Express capability
structure) in the chain.
Register:
MSICTRL
Bus:0
Device:3
Function:0
Offset:62h
Bit Attr Default Description
15:9 RV 00h Reserved.
8RO 1b
Per-vector masking capable
This bit indicates that PCI Express ports support MSI per-vector masking.
7RO 0b
64-bit Address Capable
A PCI Express Endpoint must support the 64-bit Message Address version of
the MSI Capability structure
1: Function is capable of sending 64-bit message address
0: Function is not capable of sending 64-bit message address.