Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
186 Order Number: 323103-001
3.19.2.18 INTPIN: Interrupt Pin Register
The INTPIN register identifies legacy interrupt INTx support.
3.19.2.19 MINGNT: Minimum Grant Register
.
3.19.2.20 MAXLAT: Maximum Latency Register
.
Register:INTPIN
Bus:0
Device:3
Function:0
Offset:3Dh
Bit Attr Default Description
7:0 RWO 01h
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI-Express port.
001: Generate INTA
Others: Reserved
BIOS/configuration Software has the ability to program this register once
during boot to set up the correct interrupt for the port.
Register:MINGNT
Bus:0
Device:3
Function:0
Offset:3Eh
Bit Attr Default Description
7:0 RO 00h
Minimum Grant: This register does not apply to PCI Express. It is hard-coded
to “00”h.
Register:MAXLAT
Bus:0
Device:3
Function:0
Offset:3Fh
Bit Attr Default Description
7:0 RO 00h
Maximum Latency: This register does not apply to PCI Express. It is hard-
coded to “00”h.