Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 185
PCI Express Non-Transparent Bridge
3.19.2.15 SID: Subsystem Identity (Dev#3, PCIE NTB Pri Mode)
This register identifies a particular subsystem.
3.19.2.16 CAPPTR: Capability Pointer
The CAPPTR is used to point to a linked list of additional capabilities implemented by
the device. It provides the offset to the first set of capabilities registers located in the
PCI compatible space from 40h.
3.19.2.17 INTL: Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing information
between initialization code and the device driver. This register is not used in newer
OSes and is just kept as RW for compatibility purposes.
Register:SID
Bus:0
Device:3
Function:0
Offset:2Eh
Bit Attr Default Description
15:0 RWO 0000h
Subsystem ID: This field must be programmed during BIOS initialization.
When any byte or combination of bytes of this register is written, the register
value locks and cannot be further updated.
Register:CAPPTR
Bus:0
Device:3
Function:0
Offset:34h
Bit Attr Default Description
7:0 RWO 60h
Capability Pointer
Points to the first capability structure for the device.
Register:INTL
Bus:0
Device:3
Function:0
Offset:3Ch
Bit Attr Default Description
7:0 RW 00h
Interrupt Line
This bit is RW for devices that can generate a legacy INTx message and is
needed only for compatibility purposes.