Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 183
PCI Express Non-Transparent Bridge
3.19.2.12 PB23BASE: Primary BAR 2/3 Base Address
The register is used by the processor on the primary side of the NTB to setup a 64b
prefetchable memory window.
Note: SW must program upper DW first and then lower DW. If lower DW is programmed first
HW will clear the lower DW.
Register:PB23BASE
Bus:0
Device:3
Function:0
Offset:18h
Bit Attr Default Description
63:nn RWL 00h
Primary BAR 2/3 Base
Sets the location of the BAR written by SW
Notes:
• The “nn” indicates the least significant bit that is writable. The number
of bits that are writable in this register is dictated by the value loaded
into the PBAR23SZ register by the BIOS at initialization time (before
BIOS PCI enumeration).”
• For the special case where PBAR23SZ = ‘0’, bits 63:00 are all RO=’0’
resulting in the BAR being disabled.
• These bits will appear to SW as RW.
(nn-1) :
12
RWL 00h
Reserved
Reserved bits dictated by the size of the memory claimed by the BAR.
Set by Section 3.19.3.19, “PBAR23SZ: Primary BAR 2/3 Size”
Granularity must be at least 4 KB.
Notes:
• For the special case where PBAR23SZ = ‘0’, bits 63:00 are all RO=’0’
resulting in the BAR being disabled.
• These bits will appear to SW as RO.
11:04 RO 00h Reserved
03 RO 1b
Prefetchable
BAR points to Prefetchable memory.
02:01 RO 10b
Type
Memory type claimed by BAR 2/3 is 64-bit addressable.
00 RO 0b
Memory Space Indicator
BAR resource is memory (as opposed to I/O).