Datasheet
PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
182 Order Number: 323103-001
3.19.2.10 BIST: Built-In Self Test
This register is used for reporting control and status information of BIST checks within
a PCI Express port. It is not supported by Intel
®
Xeon
®
processor C5500/C3500 series.
3.19.2.11 PB01BASE: Primary BAR 0/1 Base Address
This register is used to setup the primary side NTB configuration space
Note: SW must program upper DW first and then lower DW. If lower DW is programmed first
HW will clear the lower DW.
Register:BIST
Bus:0
Device:3
Function:0
Offset:0Fh
Bit Attr Default Description
7:0 RO 0h
BIST_TST: BIST Tests
Not supported. Hardwired to 00h
Register:PB01BASE
Bus:0
Device:3
Function:0
Offset:10h
Bit Attr Default Description
63:16 RW 00h
Primary BAR 0/1 Base
Sets the location of the BAR written by SW on a 64KB alignment
15:04 RO 00h
Reserved
Fixed size of 64KB.
03 RO 1b
Prefetchable
BAR points to Prefetchable memory.
02:01 RO 10b
Type
Memory type claimed by BAR 0/1is 64-bit addressable.
00 RO 0b
Memory Space Indicator
BAR resource is memory (as opposed to I/O).