Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
18 Order Number: 323103-001
50 NTB Port on Intel
®
Xeon
®
Processor C5500/C3500 Series Connected to Root Port - Non-
Symmetric.............................................................................................................141
51 NTB Port Connected to Non-Intel
®
Xeon
®
Processor C5500/C3500 Series System - Non-
Symmetric.............................................................................................................142
52 Intel
®
Xeon
®
Processor C5500/C3500 Series NTB Port - Nomenclature..........................144
53 Crosslink Configuration ...........................................................................................147
54 B2B BAR and Translate Setup ..................................................................................149
55 Intel
®
Xeon
®
Processor C5500/C3500 Series NTB Port - BARs......................................152
56 Direct Address Translation.......................................................................................153
57 NTB to NTB Read Request, ID translation Example......................................................155
58 NTB to RP Read Request, ID translation Example........................................................156
59 RP to NTB Read Request, ID translation Example........................................................157
60 B2B Doorbell..........................................................................................................168
61 PCI Express NTB (Device 3) Type0 Configuration Space...............................................171
62 PCI Express NTB Secondary Side Type0 Configuration Space........................................238
63 System Address Map...............................................................................................321
64 VGA/SMM and Legacy C/D/E/F Regions .....................................................................322
65 Intel
®
Xeon
®
Processor C5500/C3500 Series Only: Peer-to-Peer Illustration ..................336
66 Interrupt Transformation Table Entry (IRTE) ..............................................................345
67 ACPI Power States in G0, G1, and G2 States..............................................................350
68 Idle Power Management Breakdown of the Processor Cores (Two-Core Example) ............354
69 Thread and Core C-State Entry and Exit ....................................................................355
70 Package C-State Entry and Exit................................................................................359
71 DDR_ADR to Self-Refresh Entry................................................................................364
72 Intel
®
Xeon
®
Processor C5500/C3500 Series System Diagram .....................................373
73 IIO Error Registers .................................................................................................382
74 IIO Core Local Error Status, Control and Severity Registers..........................................383
75 IIO Global Error Control/Status Register ....................................................................384
76 IIO System Event Register.......................................................................................385
77 IIO Error Logging and Reporting Example ..................................................................386
78 Error Logging and Reporting Example........................................................................387
79 IIO Error Logging Flow............................................................................................389
80 IIO PCI Express Hog Plug Serial Interface ..................................................................410
81 MSI Generation Logic at each PCI Express Port for PCI Express Hot Plug........................412
82 GPE Message Generation Logic at each PCI Express Port for PCI Express Hot Plug ...........413
83 Active ODT for a Differential Link Example .................................................................483
84 Input Device Hysteresis...........................................................................................484
85 MSID Timing Requirement.......................................................................................494
86 VCC Static and Transient Tolerance Loadlines1,2,3,4...................................................506
87 VCC Overshoot Example Waveform...........................................................................507
88 TAP Controller State Diagram...................................................................................516
89 Processor TAP Controller Connectivity .......................................................................518
90 Processor TAP Connections ......................................................................................519
91 Boundary-Scan Port Timing Waveforms.....................................................................520