Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 177
PCI Express Non-Transparent Bridge
3RO 0
Special Cycle Enable
Not applicable to PCI Express must be hardwired to 0.
2RW 0
Bus Master Enable
When this bit is Set = 1b, the PCIE NTB will forward Memory Requests
upstream from the secondary interface to the primary interface.
When this bit is Cleared = 0b, the PCIE NTB will not forward Memory
Requests from the secondary to the primary interface and will drop all
posted memory write requests and will return Unsupported Requests UR
for all non-posted memory read requests.
Note: MSI/MSI-X interrupt Messages are in-band memory writes,
setting the Bus Master Enable bit = 0b disables MSI/MSI-X
interrupt Messages as well.
Requests other than Memory or I/O Requests are not controlled by this bit.
Default value of this bit is 0b.
1RW 0
Memory Space Enable
1: Enables a PCI Express port’s memory range registers to be decoded as
valid target addresses for transactions from primary side.
0: Disables a PCI Express port’s memory range registers (including the
Configuration Registers range registers) to be decoded as valid target
addresses for transactions from primary side.
0RWL 0
IO Space Enable
Controls a device's response to I/O Space accesses. A value of 0 disables
the device response. A value of 1 allows the device to respond to I/O
Space accesses. State after RST# is 0.
NTB does not support I/O space accesses.
Hardwired to 0
Note: This bit is locked and will appear as RO to SW
Register:PCICMD
Bus:0
Device:3
Function:0
Offset:04h
Bit Attr Default Description