Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 175
PCI Express Non-Transparent Bridge
3.19.2 Standard PCI Configuration Space (0x0 to 0x3F) - Type 0
Common Configuration Space
This section covers primary side registers in the 0x0 to 0x3F region that are common to
Bus 0, Device 3. The secondary side of the NTB is discussed in the next section and is
located on NTB Bus M, Device 0. Comments at the top of the table indicate what
devices/functions the description applies to. Exceptions that apply to specific functions
are noted in the individual bit descriptions.
Note: Several registers will be duplicated for device 3 in the three sections discussing the
three modes it operates in RP, NTB/NTB, and NTB/RP primary and secondary but are
repeated here for readability.
Note: Primary side configuration registers (device 3) can only be read by the local host.
3.19.2.1 VID: Vendor Identification Register
3.19.2.2 DID: Device Identification Register (Dev#3, PCIE NTB Pri Mode)
Register:VID
Bus:0
Device:3
Function:0
Offset:00h
Bit Attr Default Description
15:0 RO 8086h
Vendor Identification Number
The value is assigned by PCI-SIG to Intel.
Register:DID
Bus:0
Device:3
Function:0
Offset:02h
Bit Attr Default Description
15:0 RO 3721h
Device Identification Number
The value is assigned by Intel to each product. IIO will have a unique device id
for each of its PCI Express single function devices.
NTB/NTB = 3725h
NTB/RP = 3726h
Default value will show that of a RP until it is programmed to either NTB/NTB
or NTB/RP.