Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
172 Order Number: 323103-001
Table 88. IIO Bus 0 Device 3 Legacy Configuration Map (PCI Express Registers)
DID VID 00h MSIXMSGCTRL
MSIXNTPTR MSIXCAPID
80h
PCISTS PCICMD 04h TABLEOFF_BIR 84h
CCR RID 08h PBAOFF_BIR 88h
BIST HDR PLAT CLSR 0Ch
8Ch
PB01BASE
10h PXPCAP
PXPNXTPTR
PXPCAPID 90h
14h DEVCAP 94h
PB23BASE
18h DEVSTS DEVCTRL 98h
1Ch
9Ch
PB45BASE
20h
A0h
24h
A4h
28h A8h
SID SUBVID 2Ch
ACh
30h B0h
CAPPTR 34h
B4h
38h B8h
MAXLAT MINGNT INTPIN INTL 3Ch
BCh
40h C0h
44h C4h
48h C8h
4Ch CCh
50h SBAR45SZ SBAR23SZ PBAR45SZ PBAR23SZ D0h
54h PPD D4h
58h D8h
5Ch DCh
MSICTRL MSINTPTR MSICAPID 60h PMCAP E0h
MSIAR 64h PMCSR E4h
MSIDR 68h
E8h
MSIMSK 6Ch
ECh
MSIPENDING 70h
F0h
74h F4h
78h F8h
7Ch FCh