Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 171
PCI Express Non-Transparent Bridge
This section discusses the primary side registers.
Figure 61 illustrates how each PCI Express port’s configuration space appears to
software. Each PCI Express configuration space has three regions:
• Standard PCI Header - This region is the standard PCI-to-PCI bridge header
providing legacy OS compatibility and resource management.
• PCI Device Dependent Region - This region is also part of standard PCI
configuration space and contains the PCI capability structures and other port
specific registers. For the IIO, the supported capabilities are:
— Message Signalled Interrupts
— Power Management
— PCI Express Capability
• PCI Express Extended Configuration Space - This space is an enhancement
beyond standard PCI and only accessible with PCI Express aware software. The IIO
supports the Advanced Error Reporting Capability in this configuration space.
Figure 61. PCI Express NTB (Device 3) Type0 Configuration Space
PCI Header
0x00
PCI Device
Dependent
Extended
Configuration Space
0x40
0x100
0xFFF
MSICAPID
0x60
0x80
MSIXCAPID
CAPPTR
0x34
PXPCAPID
0x90
0xE0
PMCAP
ERRCAPHDR
0x150
ACSCAPHDR
XP3RUET_HDR_EXT 0x160