Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
170 Order Number: 323103-001
PBAR01BASE, SB01BASE, Offset 5ECH (CBDF), Bits All. This register does not capture
the correct values for the BDF so should not be used for debug. The returned value for
the completer ID in the Complettion packet will be incorrect. This will not impact
functional operation with Intel chipsets since we do not check this field in the
completion packet at the receiver. Other RPs outside of Intel is unknown.
PBAR01BASE, SB01BASE, Offset 70CH (USMEMMISS), Bits All. This register should
only increment upon a memory miss to the enabled NTB BARs. Bug is that it will also
increment upon receiving each CFG, IO, and message in addition to a memory BAR
miss.
Bus 0, Device 3, Function 0, Offset 06H (PCISTS), Bit 3 (INTx Status). In polling mode
BDF 030, Offset 04H, Bit 10 (INTxDisable: Interrupt Disable) will be set = ‘1’ (disabled)
and SW will poll the PCISTS INTx Status bit to see if an interrupt occurred. This
functionality is not working on A0 stepping the PCISTS INTx Status does not get set
when INTxDisable is disabled. The user will need to directly poll the PDOORBELL
register to see if an interrupt occured in polling mode.
Bus 0, Device 3, Function 0, Offset C0H (SPADSEMA4), Bit 0 (Scratchpad Semaphore).
User should be able to just set bit 0 = ‘1’ in ordere to clear the semaphore register.
Instead the user must write FFFFH in order to clear the scratchpad semaphore register.
Bus 0, Device 3, Function 0, Offset 188H (MISCCTRLSTS), Bit 1 (Inbound Configuration
enable). This bit must be set = ‘1’ in NTB/RP mode in order for the secondary side of
the NTB to accept inbound CFG cycles. This is need for the external RP to be able to
program the secondary side of the NTB.
3.18.3 Bring Up Help
This section covers commmon issues in bring up.
Bus 0, Device 3, Function 0, Offset 04H (PCICMD), Bit 2:1 (Bus Master Enable and
Memory Space Enable). In order to send memory transactions across the NTB both Bits
2:1 need to be set = “11” on both sides of the NTB. Explaination. NTB is back to back
EPs. MAE controls memory transactions downstream and BME controls memory
transactions upstream. Here is an example. CPU side1 sends memory transaction to
side 2. MAE = 1 must be set on the primary side of the NTB to get the memory
transaction downstream to the secondary side of the NTB. BME = 1 must be set on the
secondary side of the NTB to get the memory transaction upstream to the attached RP.
The same operation occurs for transactions going towards the CPU from the wire. MAE
=1 on the secondary side of the NTB and BME = 1 on the primary side of the NTB.
3.19 PCI Express Configuration Registers (NTB Primary Side)
3.19.1 Configuration Register Map (NTB Primary Side)
This section covers the NTB primary side configuration space registers.
Bus 0, Device 3, Function 0 can function in three modes: PCI Express Root Port, NTB/
NTB and NTB/RP. When configured as an NTB there are two sides to discuss for
configuration registers. The primary side of the NTB’s configuration space is located on
Bus 0, Device 3, Function 0 with respect to the Intel
®
Xeon
®
processor C5500/C3500
series and a secondary side of the NTB’s configuration space is located on some
enumerated bus on another system and does not exist as configuration space on the
local Intel
®
Xeon
®
processor C5500/C3500 series system anywhere.
The secondary side registers are discussed in Section 3.20, “PCI Express Configuration
Registers (NTB Secondary Side)”