Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 169
PCI Express Non-Transparent Bridge
3.16 MSI-X Vector Mapping
Intel
®
Xeon
®
processor C5500/C3500 series provides four MSI-X vectors which are
mapped to groups of PDOORBELL bits per Table 96, “MSI-X Vector Handling and
Processing by IIO on Primary Side”. If the OS cannot support 4 MSI-X vectors but is
capable of programming all of the MSI-X table and data registers, Section 3.21.2.1,
“PMSIXTBL[0-3]: Primary MSI-X Table Address Register 0 - 3” , Section 3.21.2.2,
“PMSIXDATA[0-3]: Primary MSI-X Message Data Register 0 - 3” then the table and data
registers should be programmed according to available vectors supported. E.g. If a
single vector is only supported then all of the table and data registers should be
programmed to the same address and data values. If two vectors are supported it
could be programmed where two table and data registers point two one address with
vector 0 and the other set of two table and data registers would be programmed to a
different address and vector 1.
The same mapping exists for the NTB/RP configuration for the secondary side of the
NTB but uses groups of SDOORBELL bits Table 98, “MSI-X Vector Handling and
Processing by IIO on Secondary Side”, Section 3.21.3.1, “SMSIXTBL[0-3]: Secondary
MSI-X Table Address Register 0 - 3” , Section 3.21.3.2, “SMSIXDATA[0-3]: Secondary
MSI-X Message Data Register 0 - 3” .
A bit has also been added if the OS cannot support four MSI-X vectors and there is no
way to program the other table and data registers. This bit can be found in
Section 3.19.3.23, “PPD: PCIE Port Definition” bit 5 for primary and Section 3.20.3.23,
“DEVCAP2: PCI Express Device Capabilities Register 2” bit 0 for secondary. In this case
the primary side PMSIXTBL0 and PMSIXDATA0 must be programmed. Hardware will
then map all PDOORBELL bit(s) to this vector. The secondary side SMSIXTBL0 and
SMSIXDATA0 must be programmed. Hardware will then map all SDOORBELL bit(s) to
this vector.
3.17 RAS Capability and Error Handling
The NTB RAS capabilities is a superset of the RP RAS capabilites with the one additional
capability. This capability is a counter to identify misses to the inbound memory
windows. See Section 3.21.1.19, “USMEMMISS: Upstream Memory Miss” for details on
this register.
3.18 Registers and Register Description
The NTB port has three distinct register sets. Primary side configuration registers,
Secondary side configuration registers, and MMIO registers that span both sides of the
NTB.
3.18.1 Additional Registers Outside of NTB Required (Per Stepping)
This section covers any registers needed to make the NTB operational that are not
directly referenced in the sections below.
3.18.2 Known Errata (Per Stepping)
This section covers NTB bugs per stepping. This is intended to provide one location user
can go to that list all known bugs.
A0 stepping: