Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
168 Order Number: 323103-001
For NTB/NTB configuration an additional register and passing mechanism has been
created to overcome the issue of back to back endpoints and will work as outlined in
the example below.
Host A wishes to send heartbeat indication to Host B to notify Host B that Host A is
alive and functional.
1. Host A sets a selected bit in the B2B Doorbell register Section 3.21.1.26,
“B2BDOORBELL: Back-to-Back Doorbell” .
2. HW on Host A senses that the B2B doorbell has been set and creates a PMW and
sends it across the link to the NTB on Host B.
Note: The default base address for B2BBAR0XLAT Section 3.21.1.26, “B2BDOORBELL: Back-
to-Back Doorbell” and SB01BASE Section 3.20.2.11, “SB01BASE: Secondary BAR 0/1
Base Address (PCIE NTB Mode)” have been set to 0 so that the memory windows will
align. The registers are RW and programmable from the local host associated with the
physical NTB if the default values are not sufficient for the user model.
3. Transaction is received by the secondary side of the NTB on the other side of the
link through the SB01BASE window.
4. HW in Host B NTB decodes the PMW as its own and sets the equivalent bits in the
Primary Doorbell register Section 3.21.1.15, “PDOORBELL: Primary Doorbell” .
5. HW upon seeing the bit(s) the Primary Doorbell being set, generates an upstream
interrupt based on if INTx or MSI or MSI-X is enabled and not masked.
Figure 60. B2B Doorbell
B2B
DOORBELL
B2B
BAR0XLAT
SB01BASE PDOORBELL
HOST B
NTB
Reset Default
0
Reset Default
0
Configured by
Host A
SB01BASE
+ 64H
HOST A
NTB
SAME
PDOORBELL SB01BASE
B2B
BAR0XLAT
B2B
DOORBELL
Reset Default
0
Reset Default
0
Configured by
Host A
SB01BASE
+ 64H
SAME
HOST A
TO
HOST B
HOST B
TO
HOST A