Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 167
PCI Express Non-Transparent Bridge
3.13 Reset Requirements
The NTB isolates two independent systems. As such, a system reset on one system
must not cause any reset activity on the second system. When one of the systems
connected through the NTB port goes down, the corresponding PCIE link goes down.
The second system will eventually detect that PCIE link down status and flush all
pending transactions to/from the system that went down.
3.14 Power Management
The NTB will provide the D0/D3 device on/off capability. In addition, the NTB port will
also support L0s state.
3.15 Scratch Pad and Doorbell Registers
Intel
®
Xeon
®
processor C5500/C3500 series supports sixteen, 32-bit scratch pad
registers, (total 64B) that are accessible through the BAR0 configuration space.
The processor supports two, 16-bit doorbell registers (PDOORBELL and SDOORBELL)
that are accessible through the BAR0 configuration space.
Interrupts (INTx, MSI and MSI-X) always travel in the upstream direction, they cannot
be used to send interrupts across the NTB. If allowed this would mean that INTx, MSI
and MSI-X would be traveling downstream from the root which is illegal. The doorbell
mechanism used to send interrupts across a NTB to overcome this specific issue and to
allow for inter processor interrupt communications.
Example of a doorbell with NTB/RP configuration:
System A wishes to off load some packet processing to System B. System A writes the
packets to the Primary BAR 2/3 window Section 3.19.2.12, “PB23BASE: Primary BAR 2/
3 Base Address” and then into System B memory space through the corresponding
Primary BAR 2/3 Translate window. Section 3.21.1.3, “PBAR2XLAT: Primary BAR 2/3
Translate”
Next a bit in the Secondary Doorbell register Section 3.21.1.17, “SDOORBELL:
Secondary Doorbell” is written to start the interrupt process. Hardware on the
secondary side of the NTB upon sensing that a doorbell bit was written generates an
upstream interrupt. The type of the interrupt is fully programmable to be either an
INTx, MSI, or MSI-X.
Upon receiving the interrupt in the local IOAPIC an ISR will do a read to the
SDOORBELL to determine what the cause of the interrupt is and then do a write back to
the same register to clear the bits that were set.
Example of a doorbell with NTB/NTB configuration: