Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
164 Order Number: 323103-001
3.10.2 Attributes
PCI Express supports two attribute hints described in Table 86.This table provides how
Intel
®
Xeon
®
processor C5500/C3500 series populates these attribute fields for
requests and completions it generates.
Table 85. PCI Express Transaction ID Handling
Field Definition IIO as Requester
IIO as
Completer
Bus Number
Specifies the bus number that the
requester resides on.
The IIO fills this field in with its
internal Bus Number that the PCI
Express cluster resides on the
IIOBUSNO: IIO Internal Bus
Number. See Section 3.6.3.17,
“IIOBUSNO: IIO Internal Bus
Number” in Volume 2 of the
Datasheet.
The IIO preserves
this field from the
request and
copies it into the
completion.
Device
Number
Specifies the device number of the
requester.
For CPU requests, the IIO fills this
field in with its Device Number that
the PCI Express cluster owns.
Device 3 in this case.
Function
Number
Specifies the function number of
the requester.
The IIO fills this field in with its
Function Number that the PCI
Express cluster owns. Function 0 in
this case.
Tag
Contains a unique identifier for
every transaction that requires a
completion. Since the PCI Express
ordering rules allow read requests
to pass other read requests, this
field is used to reorder separate
completions if they return from the
target out-of-order.
NP tx: The IIO fills this field in with
a value such that every pending
request carries a unique Tag.
NP Tag[7:5]=QPI Source
NodeID[4:2]. Bits 7:5 can be non-
zero only when 8-bit tag usage is
enabled. Otherwise, IIO always
zeros out 7:5.
NP Tag[4:0]=Any algorithm that
guarantees uniqueness across all
pending NP requests from the port.
P Tx: No uniqueness guaranteed.
Tag[7:0]=QPI Source NodeID[7:0]
for CPU requests. Bits 7:5 can be
non-zero only when 8-bit tag usage
is enabled. Otherwise, IIO always
zeros out 7:5.
Table 86. PCI Express Attribute Handling
Attribute Definition IIO as Requester IIO as Completer
Relaxed
Ordering
Allows the system to relax some of the
standard PCI ordering rules.
This bit is not
applicable and set to
zero for transactions
that Intel
®
Xeon
®
processor C5500/
C3500 series
generates on PCIE
on behalf of an
Intel
®
QPI request.
On peer-to-peer
requests, the IIO
forwards this
attribute as-is.
Intel
®
Xeon
®
processor
C5500/C3500 series
preserves this field from
the request and copies it
into the completion.
Snoop Not
Required
This attribute is set when an I/O device
controls coherency through software
mechanisms. This attribute is an
optimization designed to preserve
processor snoop bandwidth.