Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 163
PCI Express Non-Transparent Bridge
3.8.3.1 EOI
NTB is a Root Complex integrated End Point (RCiEP) with respect to the local host and
as such should not receive EOI messages from the host when configured as a NTB.
Note: Due to hardware simplification in the PCIE logic, the BIOS must set bit 26 Disable EOI
in the Section 3.19.4.20, “MISCCTRLSTS: Misc. Control and Status Register” to prevent
EOI message from being sent when configured as a NTB.
3.9 32-/64-Bit Addressing
For inbound and outbound memory reads and writes, the IIO supports the 64-bit
address format. If an outbound transaction’s address is less than 4 GB, the IIO will
issue the transaction with a 32-bit addressing format on PCI Express. Only when the
address is greater than 4 GB then IIO will initiate transaction with 64-bit addressing
format. See Section 8.0, “Power Management” for details of addressing limits imposed
by Intel
®
QuickPath Interconnect and the resultant address checks that the IIO does on
PCI Express packets it receives.
3.10 Transaction Descriptor
The PCI Express Base Specification, Revision 2.0 defines a field in the header called the
Transaction Descriptor. This descriptor comprises three sub-fields:
•Transaction ID
•Attributes
• Traffic class
3.10.1 Transaction ID
The Transaction ID uniquely identifies every transaction in the system. The Transaction
ID comprises four sub-fields described in Table 85. This table provides details on how
this field in the Express header is populated by the IIO.