Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 161
PCI Express Non-Transparent Bridge
3.8.2 Lock Support
The NTB does not support lock cycles from either side of the NTB. The local host views
the NTB as a RCiEP (primary side). The remote host views the NTB as a PCIE EP
(secondary side).
• Primary side: PCI Express-compliant software drivers and applications must be
written to prevent the use of lock semantics when accessing a Root Complex
Integrated Endpoint.
Note: If erroneous software is written and lock cycles are sent from the local Intel
®
Xeon
®
processor C5500/C3500 series host to the primary side of the NTB they will be forward
across the NTB to the secondary side and then passed along to the link partner
attached to the NTB. If the link partner is capable of responding to the illegal upstream
MRdLk request then the link partner will respond with a completion with status UR. If
the link partner cannot respond to illegal upstream MRdLk request and drops the
request, the NTBs completion time-out timer will time-out and complete the MRdLk
request with a master abort (MA).
• Secondary side: PCI Express-compliant software drivers and applications must be
written to prevent the use of lock semantics when accessing a PCI Express
Endpoint.
Note: If erroneous software is written and lock cycles are sent from the external host to the
secondary side of the NTB they will be completed by the NTB and returned with a
completion status of UR.
3.8.3 Outbound Messages Supported
Table 84 provides a list the behavior of the NTB to downstream messages supported
and not supported and appropriate behavior to these messages.