Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
158 Order Number: 323103-001
3.7 NTB Inbound Transactions
This section talks about the NTB behavior for transactions that originate from an
external agent on the PCIE link towards the PCI Express NTB port. Throughout this
chapter, inbound refers to the direction towards the CPU from I/O.
3.7.1 Memory, I/O and Configuration Transactions
Table 81 lists the memory and configuration transactions supported by the Intel
®
Xeon
®
processor C5500/C3500 series which are expected to be received from the PCI
Express NTB port.
The PCI Express NTB port does not support IO transactions.
For more specific information relating to how these transactions are decoded and
forwarded to other interfaces, see Section 6.0, “System Address Map” .
Table 81. Incoming PCI Express NTB Memory, I/O and Configuration Request/
Completion Cycles
PCI Express
Transaction
Address Space
or Message
IIO Response
Inbound Write
Requests
Memory
After address translation, packets are accepted by the NTB if targeting NTB MMIO space, or
forwarded to Main Memory, PCI Express port (local or remote) or DMI (local or remote)
depending on address.
I/O
The NTB does not claim any IO space resources and as such should never be the recipient
of an inbound IO request. If this occurs it will be returned to the requester with completion
status of UR.
Type 0
Configuration
Accepted by the NTB if targeted to the secondary side of the NTB. All other configuration
cycles are unsupported and are returned with completion status of UR.
Note: This will only be seen in case of NTB/RP. In NTB/NTB case configuration transaction
will not be seen on the wire.
Type 1
Configuration
Type 1 configurations are not supported and are returned with completion status of UR
Inbound
Completions
from Outbound
Write Request
I/O CPU will never generate an IO request to the NTB so this will never occur.
Configuration
Configuration transactions will never be sent on the wire from the NTB perspective so this
will never occur.
Note: The NTB can be the target of CPU generated configuration requests to the primary
side configuration registers.
Inbound Read
Requests
Memory
After address translation packets are accepted by the NTB if targeting NTB MMIO space or
forwarded to Main Memory, PCI Express port (local or remote), DMI (local or remote).
I/O
The NTB does not claim any IO space resources and as such should never be the recipient
of an inbound IO request. If this occurs it will be returned to the requester with completion
status of UR.
Type 0
Configuration
Accepted by the NTB if targeted to the secondary side of the bridge all other configuration
cycles are unsupported and are returned with completion status of UR.
Note: This will only be seen in case of NTB/RP. In NTB/NTB case configuration transaction
will not be seen on the wire.
Type 1
Configuration
Type 1 configurations are not supported and are returned with completion status of UR
Inbound
Completions
from Outbound
Read Requests
Memory Forward to CPU, PCI Express port (local or remote) or DMI (local or remote).
I/O CPU will never generate an IO request to the NTB so this will never occur.
Configuration
Configuration transactions will never be sent on the wire from the NTB perspective so this
will never occur.
Note: The NTB can be the target of CPU generated configuration requests to the primary
side configuration registers.