Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 157
PCI Express Non-Transparent Bridge
3.6.8 Peer-to-Peer Across NTB Bridge
Inbound transactions (both posted writes and non-posted reads) on the Intel
®
Xeon
®
processor C5500/C3500 series NTB can be targeted to either the local memory or to a
peer PCIE port on the Intel
®
Xeon
®
processor C5500/C3500 series. This allows usage
models where systems can access peer PCIE devices across the NTB port.
The NTB controller will provide a mechanism to steer transactions to either local
memory or to a peer port. For non-posted reads, the NTB port will provide a
mechanism to translate the Requester ID across the NTB port while the peer port will
provide the mechanism to translate the Requester ID for the peer traffic.
Figure 59. RP to NTB Read Request, ID translation Example
JSPJSP
HOST A HOST A
HOST B HOST B
NTB A
NTB A
RCiEP
BDF 030
RCiEP
BDF 030
PCIE EP
BDF M,0,0
PCIE EP
BDF M,0,0
MRd
Req ID 0,0,0
MRd
Req ID 0,4,0
Cmpl
Req ID 0,3,0
Cmptr ID 0,0,0
Memory Read request from
HOST A to HOST B
PCI EP captures Type 0 CFG
WR Request and uses for
requests and completions
Read
Request
Completion
RP
BDF 040
RP
BDF 040
Cmpl
Req ID 0,4,0
Cmptr ID M,0,0
MRd
Req ID 0,3,0
Cmpl
Req ID 0,0,0
Cmptr ID 0,4,0
BDF 000
BDF 000