Datasheet
PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
154 Order Number: 323103-001
The following registers are used to translate the local physical address to the remote
guest address in the remote host system map (Transactions going across NTB from
primary side to secondary side)
Section 3.19.2.12, “PB23BASE: Primary BAR 2/3 Base Address”
Section 3.19.2.13, “PB45BASE: Primary BAR 4/5 Base Address”
Section 3.21.1.1, “PBAR2LMT: Primary BAR 2/3 Limit”
Section 3.21.1.2, “PBAR4LMT: Primary BAR 4/5 Limit”
Section 3.21.1.3, “PBAR2XLAT: Primary BAR 2/3 Translate”
Section 3.21.1.4, “PBAR4XLAT: Primary BAR 4/5 Translate”
The following registers are used to translate the remote guest address map to the local
guest address or local physical address map depending on VT-d2 enabled/disabled
respectively. (Transactions going across NTB from secondary side to primary side)
Section 3.20.2.12, “SB23BASE: Secondary BAR 2/3 Base Address (PCIE NTB Mode)” ,
Section 3.20.2.13, “SB45BASE: Secondary BAR 4/5 Base Address”
Section 3.21.1.5, “SBAR2LMT: Secondary BAR 2/3 Limit”
Section 3.21.1.6, “SBAR4LMT: Secondary BAR 4/5 Limit”
Section 3.21.1.7, “SBAR2XLAT: Secondary BAR 2/3 Translate”
Section 3.21.1.8, “SBAR4XLAT: Secondary BAR 4/5 Translate”
As an example direct address translation for a packet that is transmitted from the
remote guest address into the local address map using BAR 2/3 registers.
Address detection equation:
Valid Address = ((Limit > Received Address[63:0] >= Base))
Register Values:
SB23BASE = 0000 003A 0000 0000H -- BAR 2/3 base address, placed on 4GB alignment by OS
SBAR2LMT = 0000 003A C000 0000H -- Reduce window to 3GB
Received Address = 0000 003A 00A0 0000H -- Valid address proceeds to translation equation
Received Address = 0000 003A C000 0001H -- Invalid address returned as UR
Translation equation: (Used after valid Address detection)
Translated Address = ((Received Address[63:0] & ~Sign_Extend(2^SBAR23SZ) | XLAT Register[63:0])).
For example, to translate an incoming address claimed by a 4 GB window based at
0000 003A 0000 0000H to a 4 GB window based at 0000 0040 0000 0000H.
Calculation:
Received Address[63:0] = 0000 003A 00A0 0000H
SBAR23SZ = 32 -- Sets the size of Secondary BAR 2/3 = 4GB
~Sign_Extend(2^SBAR23SZ) = ~Sign_Extend(0000 0001 0000 0000H) = ~(FFFF FFFF 0000 0000H) = 0000
0000 FFFF FFFFH)
SBAR2XLAT = 0000 0040 0000 0000H -- Base address into the primary side memory (size multiple aligned)
Translated Address = 0000 003A 00A0 0000H & 0000 0000 FFFF FFFFH | 0000 0040 0000 0000H = 0000 0040
00A0 0000H